Designed for single processor workstations, the Intel® Xeon® processor W3500 series, with intelligent performance features delivers the scalable performance necessary for premium single processor workstation experience;Intel® Core™2 processor family provides entry workstation users a functional feature set that delivers a rich workstation experience for entry design and development.
With digital workbenches, users can:
| Features and benefits: | |
| Dual-core processing, EPIC architecture, and Intel® Hyper-Threading Technology | Supports massive, multi-level parallelism for today's data-intensive workloads Provides headroom for fast access to information and real-time decision making Delivers fast responses to complex computations |
| Support for up to 512 processors and one petabyte (1024TB) RAM | Provides scalable performance for enterprise flexibility Gives IT the ability to increase processor and memory capacity as needed, in an open-ended framework |
| Up to 24MB of low-latency L3 cache | Prevents idle processing cycles with a high-bandwidth data supply to the execution cores Increases the efficiency of the memory subsystem |
| Intel® Cache Safe Technology | Automatically recovers cache after cache errors Delivers mainframe-class availability |
| Enhanced machine check architecture | Automatically detects, logs, and corrects errors Provides maximum system uptime |
| Intel® Virtualization Technology (Intel® VT) | Reduces virtualization complexity and increases performance Increases operating system compatibility |
| Demand-based switching | Dynamically reduced energy consumption during typical CPU utilization (in conjunction with enabled OS) |
| Core level lock-step | Enables one processor core to mirror the operations of the other |
The Intel Xeon 3000 processor-based servers protect critical business information and offer the performance and headroom to make employees and businesses more productive, making them ideal for small and medium business owners looking for ways to support rapid business growth on small technology budgets.
| Next-generation Intel® microarchitecture, codenamed Nehalem | Intelligent next-generation Intel® microarchitecture adapts to the workload, automatically increasing processor frequency for greater performance. |
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| Intel® Turbo Boost Technology | Better performance enabled by Intel® Turbo Boost Technology, increasing processor frequency and enabling faster speeds when conditions allow |
| Intel® Intelligent Power Technology | Lower energy costs while minimizing impact to performance by automatically putting processor and memory into the lowest available power state. |
| Integrated power gates | Power to the individual processor cores is reduced to near-zero power, independent of other operating cores. |
| Intel® Virtualization Technology | A suite of virtualization-specific hardware enhancements to Intel® processors, chipsets, and I/O devices to increase application reliability, security and overall system performance Enhancements to Intel Virtualization Technology performance that further speeds up virtual machine transition (entry/exit) times. Supports hardware assist for I/O virtualization using Intel Virtualization Technology for Directed I/O (Intel® VT-d). |
| Intel® 64 architecture | Flexibility for 64-bit and 32-bit applications and operating systems |
Intel® Xeon® processor 7400 Sequence Overview:| Intel® Xeon® processor 7400 series |
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| Hardware-assisted virtualization technology |
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| Up to 16 MB shared L3 cache |
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| Intel® 64 architecture |
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| Enhanced reliability and manageability |
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Intel® Xeon® processor 5500 Sequence Overview:
Go inside the latest innovations in Intel® Turbo Boost Technology, Intel® QuickPath Technology, and Intel® Hyper–Threading Technology.| Next-generation Intel® microarchitecture |
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| Intel® Turbo Boost Technology |
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| Intel® Intelligent Power Technology |
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| Integrated power gates |
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| Intel® Virtualization Technology (Intel® VT) |
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| Intel® Virtualization Technology FlexMigration |
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| Intel® 64 architecture |
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| DDR3 memory support up to 1333 MHz |
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| Intel® I/O Acceleration Technology (Intel® I/OAT) |
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| Enhanced reliability and manageability |
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Intel® Atom™ processors, implemented in 45nm process technology, are power-optimized to deliver robust performance per watt, making them ideal for many embedded applications such as interactive kiosks, point-of-sale terminals, in-vehicle infotainment systems, media phones, industrial automation equipment, digital security systems, and residential gateways.
These single-core processors are software-compatible with previous 32-bit Intel® architecture and complementary silicon. They include embedded lifecycle support, which protects system investments by enabling extended product availability for embedded customers.
A three-chip solution is offered with the Intel® Atom™ processor N270Δ and the mobile Intel® 945GSE Express Chipset. A two-chip solution is offered with the Intel® Atom™ processor Z5xx series and the Intel® System Controller Hub US15W.
Product Highlights:
Intel Atom processor-based netbooks and nettops offer both an easy-to-use mobile device with simple interfaces and targeted performance for a good online experience. They are rugged and compact in design, and offer the freedom and flexibility of wireless connectivity¹.
Great for Internet, these devices are an affordable option for education, photo and video viewing, social networking, voice over IP, e-mail, messaging, browsing, and numerous other Internet activities and basic applications.
All Intel® Atom™ processors feature:
Many storage, networking, and embedded applications require fast I/O throughput for optimal performance. Intel® I/O processors allow servers, workstations and storage subsystems to transfer data faster, reduce communication bottlenecks, and improve overall system performance by offloading I/O processing functions from the host CPU.
The table below provides a quick overview of the Intel I/O processor family. The Intel® IOP34x family of processors, with Intel XScale® microarchitecture, builds on more than a decade of leadership in I/O processor technology.
Features and benefits:
| Intelligent I/O processor | Offloads I/O processing functions, such as I/O interrupt processing and parity calculations, from the CPU. This allows the CPU to streamline application processing and to use other system resources, such as the system bus and memory, more effectively. |
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| On-chip cache | Improves data throughput by reducing external bus traffic. |
| Parallel transaction capabilities | Eliminates the need to use expensive proprietary controllers to handle parallel transactions and compression algorithms. |
| Single-chip design | Provides smaller packaging, simplified design, and board space cost savings. Full system-on-a-chip validation. |
| Comprehensive set of development tools | Faster time-to-market. A complete range of compilers, debuggers, commercial and open source operating systems are available from multiple vendors. |
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| Low-power Pentium® processors with MMX™ technology |
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Pentium® III processors
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| *** Intel Pentium III processor at 850/700 MHz featuring Intel® SpeedStep™ technology (1.6V/1.35V respectively). |
Sitera's network processor family, the Prism IQ2000 (shown in Figure 7), consists of four RISC cores, co-processors for lookup, order management, multi-cast support, DMA management, context management, and interfaces to both SRAM/RDRAM and a general-purpose CPU. Sitera expects the Prism to handle fast path processing and for a CPU to be designed in for slow path processing.
Lucent's network processor design is very different from the other three network processors described in this article. It is a three-chip solution for the fast path. System designers need to add a general-purpose microprocessor for slow path processing. Lucent's network processor has three parts: the functional pattern processor (FPP), the routing switch processor (RSP) and the Agere system interface (ASI). Both the FPP and RSP are programmed with 4GLs (fourth-generation languages).The idea behind the FPP is that there is a large class of network processing functions that require some sort of pattern matching. This includes parsing packets and searching through routing tables. The RSP handles all actions for a particular packet, including packet modifications like routing, and traffic management functions like queueing. The ASI is for sending and receiving slow path packets from a general purpose CPU.
Development kits are available that implement the Lucent network processor using five Xilinx Virtex FPGAs. Clocked at 33MHz, they support full duplex OC-12 interfaces. The tools are not the standard C/C++ development environment that is common with other network processors. The development kit contains:
The Application Code Library includes IP switching and routing over ATM AAL5, over Ethernet, and over Frame Relay.
Intel has become a leader in marketing network processors as part of their Internet Exchange Architecture. Currently, most network processor companies are extremely secretive about their products. Intel is the exception. Of the four network processors described in this article, Intel's IXP1200 is the only one for which you can directly download a datasheet from the Web. The IXP1200, shown in Figure 5, consists of a StrongARM processor, six RISC micro-engines, and interfaces to SRAM/SDRAM memory, PCI bus, and Intel's proprietary IX Bus. The IXP1200 has been designed to do fast path and slow path processing in one chip. The StrongARM portion of the processor can be programmed for the slow path with conventional C/C++ tools. The six micro-engines are designed for fast path processing. Each micro-engine has four hardware contexts and can context switch in a single instruction. The micro-engines are limited to 4KB of program space, which is actually quite a bit, since they are programmed in microcode.
Intel provides assembly tools for the microcode as well as a simulator for debugging the non-StrongARM parts of the IXP1200. Intel ships the IXP1200 development environment with example code for Layer 2 and Layer 3 bridging and routing.
Programming the C-5 DCP is not a small task. With the possibility of writing up to 16 different C/C++ programs for 16 processors, as well as writing microcode for the serial data processors(s), and system level code to tie everything together, a lot of effort goes into harnessing the C-5's power. C-Port's core development tools are based on the popular GNU gcc compiler and gdb debugger, modified by C-Port to work with their RISC cores. To program the RISC cores, you write from one to 16 different programs in C or C++. Then you can debug all of your programs at once using the included C-5 DCP simulator, or you can load your programs on to the C-5 DCP itself, and use gdb to debug them one CPU at a time. C-Port rounds out their development toolset with a traffic generator and performance analyzer.
C-Port provides library routines, named C-Ware, to maintain software compatibility for future generations of DCPs. These routines cover features of both the RISC cores and the co-processors, including tables, queues, buffers, protocols, switch fabrics, kernel services, and diagnostics. The C-Ware reference library includes C-5 implementations of a gigabit ethernet switch, packet over SONET (POS) switch, and ATM switch.
Since network processors are very different from general purpose processors, the most important question for programmers is, how do you program it? How do you make effective use of multiple RISC cores and hardware acceleration units? Every network processor vendor insists that their design is the easiest to program, so it is good to think critically about this question.
In many ways, network processor architectures look like the parallel processing architectures of a decade ago. Programmers have tried to harness the power of parallel processing architectures for a long time, but with little luck. Vector-processing supercomputers are used for special purpose applications like weather simulation, but programmers have not been successful in using them for general purpose applications.
Is there any reason to think network processors will fare better? Yes, there is. Network processors are not trying to speed up general purpose processing. Network processing has certain characteristics that are very different from general purpose processing. Network processing involves less code but more data than general purpose processing. There is less interdependency between the data. Consider a router again. If a router receives n packets, for a small number n, it can process those packets independently. Another way of saying this is that processing these packets doesn't change the router's state. The exception to this would be configuration packets, or routing protocol packets. However, even these interdependencies are rather loose. If a router receives a packet that indicates it should update its routing tables, there is no reason it can't finish processing a few more packets before it does the update.
Network processor architectures make CPU architectures look staid and boring. Network processor designers from different companies have made vastly different decisions about I/O interfaces, memory interfaces, and programming models, not to mention system architecture and what flavors of hardware acceleration to include.Not all network devices have the same processing requirements. However, a lot of similarities exist. As an example, I will roughly describe the packet processing duties of a router and a web switch. These core, time-critical duties are also called data plane tasks.
Routers are the workhorses of the Internet. A router accepts packets from one of several network interfaces, and either drops them or sends them out through one or more of its other interfaces. Packets may traverse a dozen or more routers as they make their way across the Internet. Here is a simplified version of the IP routing algorithm:
Web switches, by contrast, are a new type of network device. They address the problem of trying to increase the responsiveness of a popular Web site by using more than one web server. A web switch can direct incoming HTTP requests to different servers based on a variety of networking parameters, including the URL itself. For instance, all secure HTTP requests could be forwarded to a special web server with cryptographic hardware to accelerate those requests. Here is a simplified web switch algorithm:
Note that, for a given bandwidth, the web switch processing requirements are much higher, and require much more state than the router processing requirements. The difference arises because a router processes packets, but a web switch processes connections.
The previous description of the core operations of a router and a web switch were not complete. A major piece was missing. What was it? Device management. How do you configure and control this device?
A variety of less time-critical tasks fall outside the core processing or forwarding requirements of a network device. These are called control plane tasks. For a router, these tasks include routing protocols like OSPF and BGP, and management interfaces like serial ports, telnet, and SNMP. For a web switch, these tasks include receiving updates about the status of web servers and providing a web interface for configuration and management. For both devices, error handling and logging are important control plane tasks.
Another way to distinguish data plane tasks from control plane tasks is to look at each packet's path. Packets handled by data plane tasks usually travel through the device, while packets handled by control plane tasks usually originate or terminate at the device.
Major semiconductor manufacturers are starting to sell a new type of integrated circuit, the network processor. Network processors are programmable chips like general purpose microprocessors, but are optimized for the packet processing required in network devices.
Network devices are a growing class of embedded system and include traditional Internet equipment like routers, switches, and firewalls; newer devices like Voice over IP (VoIP) bridges, virtual private network (VPN) gateways, and quality of service (QOS) enforcers; and web-specific devices like caching engines, load balancers, and SSL accelerators.
